Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Digital storage, addition and subtraction of time-mode variables

Digital storage, addition and subtraction of time-mode variables

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

Presented are novel digital methods to perform storage, addition and subtraction of time-mode variables. The concept of a switched delay unit is introduced and by adopting this key element, the instantaneous phase difference between two rising edges can be latched and used to perform various arithmetic operations. The proposed technique can be used to implement analogue sampled-data signal processing using digital circuitry. Simulation results are provided.

Inspec keywords: digital circuits; signal processing; digital storage

Other keywords: addition; digital circuitry; digital storage; arithmetic operations; subtraction; rising edges; switched delay unit; time-mode variables; instantaneous phase difference; analogue sampled-data signal processing

Subjects: Digital signal processing; Signal processing and detection; Digital storage; Digital electronics

References

    1. 1)
      • Ravinuthula, V., Harris, J.G.: `Time-based arithmetic using step functions', IEEE Int. Symp. on Circuits and Systems, May 2004, Vancouver, BC, Canada, p. 305–308.
    2. 2)
      • Ying, C., Leroux, P., De Cock, W., Steyaert, W.M.: `A 1.7 mW 11b 1–1–1 MASH ΔΣ time-to-digital converter', IEEE Int. Solid-State Circuits Conf., (ISSCC), Dig. Tech. Pprs, February 2011, San Francisco, CA, USA, p. 480–482.
    3. 3)
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2011.1406
Loading

Related content

content/journals/10.1049/el.2011.1406
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address