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A novel time-difference amplifier (TDA) is presented. The proposed circuit has a larger linear operation region with less sensitivity to process variations than the state-of-the-art TDAs. Two TDAs with gains of two and 20 have been simulated in a 65 nm CMOS process to validate the proposed architecture. Simulation results show less than 0.1% gain error for ±400 ps input time difference range, ten times the range of conventional TDAs. The proposed TDA consumes 740 µW from a 1 V supply.
References
-
-
1)
-
A.M. Abas ,
A. Bystrov ,
D.J. Kinniment ,
O.V. Maevsky ,
G. Russell ,
A.V. Yakovlev
.
Time difference amplifier.
Electron. Lett.
,
23 ,
1437 -
1438
-
2)
-
M. Safi-Harb ,
G.W. Roberts
.
70-GHz effective sampling time based on-chip oscilloscope in CMOS.
IEEE J. Solid-State Circuits
,
8 ,
1743 -
1757
-
3)
-
M. Lee ,
A.A. Abidi
.
A 9b 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue.
IEEE J. Solid-State Circuits
,
769 -
777
-
4)
-
S.-K. Lee
.
A 1 GHz ADPLL with a 1.25 ps minimum-resolution sub exponent TDC in 0.18 µm CMOS.
IEEE J. Solid-State Circuits
,
12 ,
2874 -
2881
-
5)
-
Oulmane, M., Roberts, G.W.: `A CMOS time amplifier for femtosecond resolution timing measurement', Proc. IEEE Int. Symp. Circuits and Systems, (ISCAS), 2004, Vancouver, BC, Canada, p. 509–512.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2011.1279
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content/journals/10.1049/el.2011.1279
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