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An energy-efficiency floating-capacitor switching (FCS) scheme is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By rearranging the switching order from the smallest capacitor to the largest one, the switching energy can be significantly reduced, especially in the first several DAC switchings. With the presented scheme, a 97.66% less switching energy can be achieved compared to the conventional architecture (Ginsburg and Chandrakasan, 2005 [4]).
References
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1)
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Ginsburg, B.P., Chandrakasan, A.P.: `An energy-efficient charge recycling approach for a SAR converter with capacitive DAC', IEEE Int. Symp. on Circuits and Systems, May 2005, Kobe, Japan, p. 184–187.
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2)
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Chang, Y.K., Wang, C.S., Wang, C.K.: `A 8-bit 500-KS/s low power SAR ADC for bio-medical applications', IEEE Asian Solid-State Circuits Conf., November 2007, Jeju, Korea, p. 228–231.
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3)
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Y. Zhu
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A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS.
IEEE J. Solid-State Circuits
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1121
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4)
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C. Liu
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A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure.
IEEE J. Solid-State Circuits
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4 ,
731 -
740
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2011.0822
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