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Settling optimised sample-and-hold circuit with high-linearity input switch in 65 nm CMOS

Settling optimised sample-and-hold circuit with high-linearity input switch in 65 nm CMOS

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Published

A settling optimised sample-and-hold (SH) circuit with a wideband high-linearity input switch is presented. A proposed input switch with floating-well isolation achieves low on-resistance and high-linearity through a wide input frequency range. A method for the SH to acquire the optimised settling behaviour by choosing a feedback switch with suitable on-resistance is proposed to achieve low-power target. Simulation results show that the performance of the SH is improved considerably.

Inspec keywords: sample and hold circuits; CMOS analogue integrated circuits

Other keywords: CMOS; optimised sample-and-hold circuit; size 65 nm; wideband high-linearity input switch; floating-well isolation

Subjects: Other analogue circuits; Analogue circuits; CMOS integrated circuits; Analogue storage

References

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      • A. Zanchi , D.Y. Chang . A 16-bit 65-MS/s pipeline ADC with 80-dBFS SNR using analog auto-calibration in SiGe SOI complementary BiCMOS. IEEE Trans. Circuits Syst. II, Reg Pprs , 2166 - 2177
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      • W. Yang , D. Kelly , I. Mehr , M. Sayuk , L. Singer . A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE J. Solid-State Circuits , 1931 - 1936
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