Settling optimised sample-and-hold circuit with high-linearity input switch in 65 nm CMOS

Settling optimised sample-and-hold circuit with high-linearity input switch in 65 nm CMOS

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A settling optimised sample-and-hold (SH) circuit with a wideband high-linearity input switch is presented. A proposed input switch with floating-well isolation achieves low on-resistance and high-linearity through a wide input frequency range. A method for the SH to acquire the optimised settling behaviour by choosing a feedback switch with suitable on-resistance is proposed to achieve low-power target. Simulation results show that the performance of the SH is improved considerably.


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