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Decoupled 4T dynamic CAM suitable for high density storage

Decoupled 4T dynamic CAM suitable for high density storage

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A new four-transistor dynamic CAM (DCAM) is introduced. The DCAM design addresses the inherent data retention problem by proposing a modified sensing scheme. The results indicate over an order of magnitude improvement in data retention time. In addition, the DCAM structure realises a decoupled match-line structure, which enables high density configurations not possible from previous 4T CAM approaches.

References

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      • Barth, J., Plass, D., Nelson, E., Hwang, C., Gredeman, G., Sperling, M., Mathews, A., Reohr, W., Nari, K., Cae, N.: `A 45 nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache', Int. Solid-State Circuits Conf., February 2010, San Francisco, CA, USA, p. 342–343.
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      • Delgado-Frias, J.G., Yu, A., Nyathi, J.: `A dynamic content addressable memory using a 4-transistor cell', 3rdInt. Workshop on Design of Mixed-Mode Integrated Circuits and Applications, 1999, Puerto Vallarta, Mexico, p. 110–113.
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