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An SRAM design in a 3D 0.18 µm silicon-on-insulator technology is presented. A novel delay-locked loop based access time measurement circuit was designed on-chip for accurately evaluating the 3D SRAM performance. Results show that a 32% improvement in the access time is gained by using 3D technology.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2010.3701
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content/journals/10.1049/el.2010.3701
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