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Three-dimensional SRAM design with on-chip access time measurement

Three-dimensional SRAM design with on-chip access time measurement

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An SRAM design in a 3D 0.18 µm silicon-on-insulator technology is presented. A novel delay-locked loop based access time measurement circuit was designed on-chip for accurately evaluating the 3D SRAM performance. Results show that a 32% improvement in the access time is gained by using 3D technology.

References

    1. 1)
    2. 2)
      • Tsai, Y.-F., Xie, Y., Vijaykrishnan, N., Irwin, M.J.: `Three-dimensional cache design exploration using 3D cacti', Proc. Int. Conf. on Computer Design, 2005, Las Vegas, NV, USA, p. 519–524.
    3. 3)
    4. 4)
      • Chen, X., Davis, W.R.: `Delay analysis and design exploration for 3D SRAM', IEEE Int. Conf. on 3D System Integration, September 2009, San Francisco, CA, USA.
    5. 5)
      • MIT Lincoln Laboratory: ‘MITLL Low-Power FDSOI CMOS Process Design Guide, Revision 2008:5’, Sep. 2008.
    6. 6)
    7. 7)
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