© The Institution of Engineering and Technology
Proposed is a new selective negative word line scheme that yields almost 2.7% of the fail bit count (FBC) in a DRAM chip with a conventional negative word line scheme in the pause refresh state. It has a superior dynamic refresh characteristic, which is almost 0.3% of the FBC in a DRAM chip using the ground word line scheme. This scheme leads to a very low cell VTH (threshold voltage).
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http://iet.metastore.ingenta.com/content/journals/10.1049/el.2010.3643
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