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Selective negative word line scheme for improving refresh

Selective negative word line scheme for improving refresh

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Proposed is a new selective negative word line scheme that yields almost 2.7% of the fail bit count (FBC) in a DRAM chip with a conventional negative word line scheme in the pause refresh state. It has a superior dynamic refresh characteristic, which is almost 0.3% of the FBC in a DRAM chip using the ground word line scheme. This scheme leads to a very low cell VTH (threshold voltage).

References

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      • Lee, M.J., Kyung, K.M., Won, H.S., Lee, M.S., Park, K.W.: `A bitline sense amplifier for offset compensation', International Solid-State Circuits Conf., no. 24.4, February 2010, San Francisco, CA, USA, p. 438–439.
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      • Nagai, Y., Wada, M., Iwai, H., Kaku, M., Suzuki, A., Takai, T., Itoga, N., Miyazaki, T., Takenaka, H., Hojo, T., Miyano, S.: `A 65 nm low-power embedded DRAM with extended data retention sleep mode', Int. Solid-State Circuits Conf., February 2006, San Francisco, CA, USA, p. 567–568.
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      • Lee, M.J., Ahn, J.H.: `Semiconductor memory device and driving method thereof', United States patent, US2010/0046313 A1, February 2010.
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