Subthreshold voltage startup module for stepup DC–DC converter

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Subthreshold voltage startup module for stepup DC–DC converter

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Published

The design of a subthreshold voltage startup module for low input voltage applications, down to 0.55 V, is introduced. The proposed startup module can generate a relatively high voltage from input to assist a stepup DC–DC converter to start. It employs a dynamic substrate biasing technique to realise subthreshold operation. The design was verified by simulation and measurement in a commercial 0.35 µm CMOS process.

Inspec keywords: DC-DC power convertors; CMOS integrated circuits

Other keywords: stepup DC-DC converter; low input voltage applications; dynamic substrate biasing technique; CMOS process; subthreshold voltage startup module design; size 0.35 mum

Subjects: Power electronics, supply and supervisory circuits; CMOS integrated circuits

References

    1. 1)
      • T.M. Van Breussegem . Area-driven optimisation of switched-capacitor DC/DC converters. Electron. Lett. , 25 , 1488 - 1490
    2. 2)
      • J. Larminie , A. Dicks . (2003) Fuel cells systems explained.
    3. 3)
      • J.H. Lou , J.B. Kuo . A 1.5-V full–swing bootstrapped CMOS large capacitive–load driver circuit suitable for low–voltage CMOS VLSI. IEEE J. Solid–State Circuits , 1 , 119 - 121
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