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Phase-locked loop based delta-sigma ADC

Phase-locked loop based delta-sigma ADC

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Published

A phase-locked loop (PLL) based delta-sigma analogue-to-digital converter architecture providing second-order noise shaping is presented. By combining a low power passive integrator with a voltage-controlled oscillator-based integrator, the proposed architecture suppresses the oscillator nonlinearity with minimum hardware penalty. Simulation results indicate 14-bit performance by using only a 4-bit linear oscillator.

Inspec keywords: voltage-controlled oscillators; delta-sigma modulation; phase locked loops

Other keywords: low power passive integrator; phase-locked loop; analogue-to-digital converter; PLL; voltage-controlled oscillator; 4-bit linear oscillator; delta-sigma ADC; second-order noise shaping

Subjects: A/D and D/A convertors; Modulators, demodulators, discriminators and mixers; Oscillators

References

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      • P. Hanumolu , M. Brownlee , K. Mayaram , U.-K. Moon . Analysis of charge-pump phase-locked loops. IEEE Trans. Circuits Syst I: Regular Papers , 9 , 1665 - 1674
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      • J. Kim , T.-K. Jang , Y.-G. Yoon , S. Cho . Analysis and design of voltage-controlled oscillator-based analog-to-digital converter. IEEE Trans. Circuits and Syst. I: Regular Papers , 1 , 18 - 30
    3. 3)
      • M. Hovin , A. Olsen , T. Lande , C. Toumazou . Delta-sigma modulators using frequency-modulated intermediate values. IEEE J. Solid-State Circuits , 1 , 13 - 22
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      • M. Straayer , M. Perrott . A 12-Bit, 10-MHz bandwidth, continuous-time ΣΔ ADC with a 5-Bit, 950-MS/s VCO-based quantizer. IEEE J. Solid-State Circuits , 4 , 805 - 814
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      • Park, M., Perrott, M.: `A 0.13 µm CMOS 78 dB SNDR 87 mW 20 MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer', IEEE Int. Solid-State Circuits Conf.-Digest of Technical Papers, 2009. ISSCC 2009., February 2009, San Francisco, CA, USA, p. 170–171,171a.
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