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On-chip process variation monitoring circuit based on gate leakage sensing

On-chip process variation monitoring circuit based on gate leakage sensing

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A novel on-chip process-variation monitoring circuit for nanoscale CMOS designs is proposed. The proposed circuit can monitor both global and local variations associated with transistors on an integrated circuit. The process variation is monitored by gate-tunnelling-leakage sensing with weak temperature dependence, which solves the problem of the strong temperature dependence of the conventional subthreshold leakage sensing. The proposed circuit with low power dissipation (1.92 µW at 85°C) is implemented using 45 nm technology, and the results show that it monitors only the process variation with weak dependence (within 5%) on VDD and temperature variations.

References

    1. 1)
      • Rigorous extraction of process variations for 65-nm CMOS design
    2. 2)
      • Kim, C.H., Roy, K., Hsu, S.: `An on-die CMOS leakage current sensor for measuring process variation in sub-90nm generations', IEEE Int. Conf. on IC Design and Technology (ICICDT), May 2005, p. 221–222
    3. 3)
      • Datta, B., Burleson, W.: `Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors', IEEE GLSVLSI, Bostan, MA, USA, p. 145–148
    4. 4)
      • Yang, S., Wolf, W.: `Accurate stacking macro-modeling of leakage power in sub-100 nm circuits', Proc. IEEE VLSID, 2005, Kolkata, India, p. 165–170
    5. 5)
      • Shima, T.: `Temperature insensitive current reference circuit using standard CMOS devices', IEEE MWSCAS'07, August 2007, Montreal, Canada, p. 181–184
    6. 6)
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