On-chip process variation monitoring circuit based on gate leakage sensing

On-chip process variation monitoring circuit based on gate leakage sensing

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A novel on-chip process-variation monitoring circuit for nanoscale CMOS designs is proposed. The proposed circuit can monitor both global and local variations associated with transistors on an integrated circuit. The process variation is monitored by gate-tunnelling-leakage sensing with weak temperature dependence, which solves the problem of the strong temperature dependence of the conventional subthreshold leakage sensing. The proposed circuit with low power dissipation (1.92 µW at 85°C) is implemented using 45 nm technology, and the results show that it monitors only the process variation with weak dependence (within 5%) on VDD and temperature variations.


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