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Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies

Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies

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© The Institution of Engineering and Technology
Published

An asymmetric 6T-SRAM cell design is presented for reliable low-power circuit operation under large variability. A low overhead write assist circuit is added to increase the write-noise-margin (WNM) and improve the write speed/power. Sizing is used to strengthen the pull-down transistor of the feedback inverter of the single ended read circuit to enhance the static-noise-margin (SNM). Monte Carlo simulations indicate a 90% improvement in SNM and a boost in the WNM of 108% compared to the conventional 6T-SRAM design. Comparative analysis of a 65nm 64×32 bit SRAM designed using both SRAM cells (Symmetric-6T and Asymmetric-6T) shows the write delay and power decrease by 46% and 35%, respectively, while total power decreases by 52% using the proposed design.

Inspec keywords: CMOS memory circuits; Monte Carlo methods; integrated circuit noise; nanoelectronics; integrated circuit design; SRAM chips; circuit simulation

Other keywords: size 65 nm; static-noise-margin; nanoCMOS technology; write power; write speed; feedback inverter; low-power circuit operation; static random access memory; Monte Carlo simulations; total power; write-noise-margin; single ended read circuit; storage capacity 64 bit; pull-down transistor; storage capacity 32 bit; write delay; complementary metal-oxide-semiconductor; low overhead write assist circuit; robust asymmetric 6T-SRAM cell design

Subjects: Computer-aided circuit analysis and design; Semiconductor integrated circuit design, layout, modelling and testing; Digital circuit design, modelling and testing; Nanometre-scale semiconductor fabrication technology; Monte Carlo methods; Memory circuits; CMOS integrated circuits

References

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