High-resolution time-to-digital converter utilising fractional difference conversion scheme

High-resolution time-to-digital converter utilising fractional difference conversion scheme

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A high-resolution process, voltage and temperature (PVT)-insensitive time-to-digital converter (TDC) is presented, based on a Vernier delay-line, in which the propagation delays in the upper and lower buffer chains are stabilised by two different delay-locked-loops (DLLs). The limitation on its resolution, imposed by DLL jitter and input range of time intervals, is analysed. Simulation results show that the proposed TDC achieves a resolution as high as 22.7 ps while consuming only 2.7 mW.


    1. 1)
    2. 2)
      • C.-S. Hwang , P. Chen , H.-W. Tsao . A high-precision time-to-digital converter using a two-level conversion scheme. IEEE Trans. Nucl. Sci. , 1349 - 1352
    3. 3)
      • Kim, B., Weigandt, T.C., Gray, P.R.: `PLL/DLL system noise analysis for low jitter clock synthesizer design', Proc. Int. Symp. on Circuits and Systems, June 1994, London, UK, 4, p. 31–34.
    4. 4)
      • Heydari, P.: `Analysis of DLL jitter due to substrate noise', Proc. IEEE Custom Integrated Circuits Conf., August 2008, Łódź, Poland, p. 348–351.
    5. 5)
      • M. Badaroglu , P. Wambacq , G. Van der Plas , S. Donnay , G.G.E. Gielen , H.J. De Man . Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. , 2 , 296 - 305

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