http://iet.metastore.ingenta.com
1887

High-resolution time-to-digital converter utilising fractional difference conversion scheme

High-resolution time-to-digital converter utilising fractional difference conversion scheme

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A high-resolution process, voltage and temperature (PVT)-insensitive time-to-digital converter (TDC) is presented, based on a Vernier delay-line, in which the propagation delays in the upper and lower buffer chains are stabilised by two different delay-locked-loops (DLLs). The limitation on its resolution, imposed by DLL jitter and input range of time intervals, is analysed. Simulation results show that the proposed TDC achieves a resolution as high as 22.7 ps while consuming only 2.7 mW.

References

    1. 1)
    2. 2)
      • C.-S. Hwang , P. Chen , H.-W. Tsao . A high-precision time-to-digital converter using a two-level conversion scheme. IEEE Trans. Nucl. Sci. , 1349 - 1352
    3. 3)
      • Kim, B., Weigandt, T.C., Gray, P.R.: `PLL/DLL system noise analysis for low jitter clock synthesizer design', Proc. Int. Symp. on Circuits and Systems, June 1994, London, UK, 4, p. 31–34.
    4. 4)
      • Heydari, P.: `Analysis of DLL jitter due to substrate noise', Proc. IEEE Custom Integrated Circuits Conf., August 2008, Łódź, Poland, p. 348–351.
    5. 5)
      • M. Badaroglu , P. Wambacq , G. Van der Plas , S. Donnay , G.G.E. Gielen , H.J. De Man . Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. , 2 , 296 - 305
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2010.2698
Loading

Related content

content/journals/10.1049/el.2010.2698
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address