In conventional fractional N phase-locked loops (PLLs), charge pump nonlinearity dominates the overall loop linearity. A nonlinear charge pump increases close-in phase noise and fractional spur. Charge pump nonlinearity is mainly caused by up and down current mismatch which is in turn caused by device mismatch, and finite output impedance. A new charge pump linearisation technique is proposed by introducing an extra delay in the phase-frequency detector (PFD), so that charge nonlinearity caused by current mismatch is cancelled. The new method is independent of current mismatch. A fractional N PLL has been implemented in a 0.18 µm CMOS technology with the proposed linearisation technique. The measured fractional spur at 300 kHz offset is −77 dBc at 3.975 GHz.