Test data compression using extended frequency-directed run length code based on compatibility

Test data compression using extended frequency-directed run length code based on compatibility

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A new test data compression method is presented. Based on the fact that adjacent test vectors in a test set have least incompatible bits, test vectors are grouped and amalgamated into a vector by assigning 1 or 0 to unspecified bits and c to incompatible bits. Extended frequency-directed run length based on compatibility (EFDR-BC) is used to encode the merged test vector. EFDR-BC can encode strings of 1s, 0s, and cs. The numbers of test vectors, incompatible bits and values of incompatible bits in a group make up the group head code. Experiments with the test sets of the ISCAS 89 benchmark circuit show that the method can achieve higher compression ratio.


    1. 1)
    2. 2)
      • Konemann, B.: `LFSR-coded test patterns for scan designs', Proc. Euro. Test Conf., 1991, p. 237–242.
    3. 3)
    4. 4)
      • Chandra, A., Chakrabarty, K.: `Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression', Proc. VTS, 2001, p. 42–47.
    5. 5)
      • El-maleh, A., Al-Abaji, R.: `Extended frequency directed run length codes with improved application to system-on-a-chip test data compression', Proc. Int. Conf. Electronic Circuits and Systems, 2002, p. 449–452.
    6. 6)
      • X. Kavousianos , E. Kalligeros , D. Nikolos . Multilevel-Huffman test-data compression for IP cores with multiple scan chains. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 7 , 926 - 931
    7. 7)
    8. 8)
    9. 9)
      • Jas, A., Touba, N.A.: `Test vector decompression via cyclical scan chains and its application to testing core-based design', Proc. ITC, 1998, p. 458–464.
    10. 10)
      • A.H. El-maleh . Efficient test compression technique based on block merging. IET Comput. Digital Tech. , 5 , 327 - 335

Related content

This is a required field
Please enter a valid email address