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Two-step split-junction SAR ADC

Two-step split-junction SAR ADC

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A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analogue-to-digital converters (SAR ADCs). Two split-junction binary-weighted capacitor arrays are used in a coarse/fine quantisation scheme. This reduces both the power consumption and the capacitor area to a small fraction of that of the original split-junction SAR ADC.

References

    1. 1)
      • Analog integrated circuit design
    2. 2)
      • Lee, J.S., Park, I.C.: `Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters', Proc. Int. Symp. on Circuits and Systems, May 2008, Seattle, WA, USA, p. 236–239
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2010.2392
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