Your browser does not support JavaScript!

Three-level differential buffer for increasing noise margin in pseudo-differential signalling

Three-level differential buffer for increasing noise margin in pseudo-differential signalling

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A 5Gbit/s/pin transceiver for high-speed memory interfaces is implemented in a 0.18 µm CMOS process. In general, memory interfaces use single-ended signalling with a reference signal because the chip cost is closely related to the number of pins. However, as the data rate increases, reference voltage noise and simultaneous switching noise reduce voltage and timing margin of receiver input signals. Pseudo-differential signalling (PDS) is used to solve the problems, however a previous receiver using PDS is sensitive to core power noise because the receiver uses three-level signals with reduced noise margin. The three-level differential buffer (TLDB) which is robust to core power noise is proposed and the noise margin of the TLDB outputs is larger than that of outputs of a previous PDS receiver.


    1. 1)
      • Bae, S-J., Shon, Y.-S., Park, K.-I.: `A 60 nm 6 Gb/s/pin GDDR5 graphics DRAM with multifaced clocking and ISI/SSN-reduction techniques', ISSCC Dig. Tech. Pprs., February 2008, Grenoble, France, p. 278–279.
    2. 2)
      • Ha, K.-S., Kim, L.-S.: `A 3.2-Gb/s transceiver with a quarter-rate linear phase detector reducing the phase offset', Proc. IEEE ASSCC, November 2008, Fukuoka, Japan, p. 217–220.
    3. 3)
      • K.-S. Ha , L.-S. Kim , S.-J. Bae . A 0.13-µm CMOS 6 Gb/s/pin memory transceiver using pseudo-differential signaling for removing common-mode noise due to SSN. IEEE J. Solid-State Circuits , 11 , 3146 - 3162
    4. 4)
      • S.-J. Bae , K.-I. Park , J.-D. Ihm . An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 graphics DRAM with low power and low noise data bus inversion. IEEE J. Solid-State Circuits , 1 , 121 - 131
    5. 5)
      • S. Zogopoulos , W. Namgoong . High-speed single-ended parallel link based on three-level differential encoding. IEEE J. Solid-State Circuits , 2 , 549 - 557
    6. 6)
      • H.L. Zapf . DC transfer characteristic offset voltage sensitivities and CMRR of FET differential states. IEEE J. Solid-State Circuits , 2 , 262 - 265

Related content

This is a required field
Please enter a valid email address