Check-bit-reduced codewords using non-2n data bits for ECC-based self-refresh enhancement techniques in DRAMs

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Check-bit-reduced codewords using non-2n data bits for ECC-based self-refresh enhancement techniques in DRAMs

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© The Institution of Engineering and Technology
Published

Error correction code (ECC) techniques have often been used to reduce the self-refresh power of dynamic random access memories (DRAMs). However, the overhead associated with the large number of check bits has prevented ECC methods from being incorporated into commercial applications. In a novel approach employed in this reported work, the number of data bits in the proposed codeword is set to have a length that is not a power of two (non-2n). Such a condition results in a substantial decrease in the number of required check bits. Compared to the use of 2n data bits in 1 Gb DRAMs, implementations that utilise the proposed codeword can achieve ECC-enhanced self-refresh schemes with 3.4 and 4.7% reductions in check bit and register overheads, respectively.

Inspec keywords: error correction codes; random-access storage

Other keywords: dynamic random access memories; DRAM; ECC-based self-refresh enhancement; check-bit-reduced codewords; self-refresh power; non-2n data bits; error correction code

Subjects: Codes; Memory circuits; Semiconductor storage

References

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