© The Institution of Engineering and Technology
A novel topology for frequency synthesis using digital-to-frequency conversion and a filtering technique is presented. The implementation uses a high-order digital sigma–delta modulator to encode a DC value, which is then mapped to a corresponding frequency using a digital-to-frequency conversion algorithm. The output bit-sequence with the sigma–delta encoded frequency is then applied to a high-order phase-locked loop (PLL) behaving as a filter operating on the incoming instantaneous frequency. The theory of the proposed scheme is described and validated with simulation and experiment. A prototype board-level implementation with a sixth-order PLL was constructed and frequencies ranging from 30.5 to 44.5 MHz were experimentally generated with a 25 kHz resolution from a single 100 MHz master clock.
References
-
-
1)
-
M.H. Perrott
.
A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis.
IEEE J. Solid-State Circuits
,
1028 -
1038
-
2)
-
B. De Muer ,
M. Steyaert
.
(2003)
CMOS fractional-N synthesizers.
-
3)
-
Almeida, T.M., Piedade, M.S.: `High performance analog and digital PLL design', Proc. ISCAS, 1999, Orlando, FL, USA, 4, p. 394–397.
-
4)
-
T.A. Riley ,
M. Copeland ,
T. Kwasniewski
.
Delta-sigma modulation in fractional-N frequency synthesis.
IEEE J. Solid-State Circuits
,
553 -
559
-
5)
-
W. Chen ,
M.A. Thornton ,
P. Gui
.
Redundant signed binary addition based digital-to-frequency converter.
Electron. Lett.
,
824 -
826
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2010.1344
Related content
content/journals/10.1049/el.2010.1344
pub_keyword,iet_inspecKeyword,pub_concept
6
6