http://iet.metastore.ingenta.com
1887

Triple-bit method for power estimation of nonlinear digital circuits in FPGAs

Triple-bit method for power estimation of nonlinear digital circuits in FPGAs

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Power consumption of many of the digital signal processing systems available is nonlinear. Signal distribution at the multiplier output changes significantly with respect to its input signal distributions. Data signals have a large impact on design power, so the multiplier output has to be modelled properly. A model to compute the bit-level switching activity of each multiplier output bit is presented. This model depends on word-level signal statistics and the number of multiplied input signals. It is applied to high-level power estimation of FPGA designs. The relative errors of the presented power model with respect to measured power are four to five times smaller than the errors obtained by using the standard signal model for high-level power estimation.

References

    1. 1)
    2. 2)
    3. 3)
      • J.C. Pedro , N.B. Carvalho . (2003) Intermodulation distortion in microwave and wireless circuits.
    4. 4)
    5. 5)
      • Kyriakis-Bitzaros, D., Nikolaidis, S.: `Estimation of bit-level transition activity in data-paths based on word-level statistics and conditional entropy', IEE Proc. Circuits Devices Syst., 2002, 149, p. 234–240.
    6. 6)
      • R. Jevtic , C. Carreras , G. Caffarena . Fast and accurate power estimation of FPGA DSP components based on high-level switching activity models. Int. J. Electron. , 7 , 653 - 658
    7. 7)
      • R. Jevtic , C. Carreras . Power measurement methodology for FPGA devices. IEEE Trans. Instrum. Meas. , 9
    8. 8)
      • R. Jevtic , C. Carreras . Power estimation of embedded multiplier blocks in FPGAs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 5 , 835 - 839
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2010.0790
Loading

Related content

content/journals/10.1049/el.2010.0790
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address