Low-power L2 cache design for multi-core processors

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Low-power L2 cache design for multi-core processors

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A low-power set-associative L2 cache design for a multi-core processor is proposed. Since this way-predicting L2 cache (WP-L2) predicts a destination way and accesses only the predicted way, it consumes less energy than a conventional set-associative L2 cache. Exploiting access patterns of an L2 cache, WP-L2 is based on two prediction logics; a look-ahead buffer (LAB) predicts the next sequential cache block and a way-affinity table (WAT) records the way number of the previous L2 cache access. Combining the logics, WP-L2 predicts correct ways for about 83% of L2 cache accesses and reduces about 22% of access latency and 44% of energy consumption compared to the conventional eight-way set-associative L2 cache.

Inspec keywords: power consumption; microprocessor chips; cache storage; network synthesis

Other keywords: WAT; LAB; L2 cache design; look-ahead buffer; multicore processors; way-affinity table; energy consumption

Subjects: Microprocessor chips; Microprocessors and microcomputers; Digital circuit design, modelling and testing; Semiconductor storage; Memory circuits

References

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      • Shivakumar, P., Jouppi, N.P.: `CACTI 3.0: an integrated cache timing, power, and area model', WRL Res. Rep. 2001/2, 2001.
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      • Kim, D., Ha, S., Gupta, R.: `CATS: cycle accurate transaction-driven simulation with multiple processor simulators’.', Proc. of DATE, 2007, Nice Acropolis, France, p. 749–754.
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      • Brooks, D., Tiwari, V., Martonosi, M.: `Wattch: a framework for architectural-level power analysis and optimizations’.', Proc. of ISCA, 2000, Vancouver, BC, Canada, p. 83–94.
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