Design of multipliers for GF(2m)
Design of multipliers for GF(2m)
- Author(s): Z. Mao ; G. Shou ; Y. Hu ; Z. Guo
- DOI: 10.1049/el.2010.0246
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- Author(s): Z. Mao 1 ; G. Shou 1 ; Y. Hu 1 ; Z. Guo 1
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View affiliations
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Affiliations:
1: School of Information and Communication Engineering, Beijing University of Posts and Telecommunications, Beijing, People's Republic of China
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Affiliations:
1: School of Information and Communication Engineering, Beijing University of Posts and Telecommunications, Beijing, People's Republic of China
- Source:
Volume 46, Issue 6,
18 March 2010,
p.
419 – 420
DOI: 10.1049/el.2010.0246 , Print ISSN 0013-5194, Online ISSN 1350-911X
A new design of multipliers for GF(2m) based on combination of bit-serial and bit-parallel schemes with low complexity is proposed. Using pipeline architecture, the scheme yields significantly lower latency compared to known bit-parallel multipliers for GF(2m).
Inspec keywords: logic design; multiplying circuits; Galois fields; pipeline processing
Other keywords:
Subjects: Algebra; Logic and switching circuits; Logic circuits; Logic design methods; Digital circuit design, modelling and testing; Parallel architecture; Algebra
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