Design of multipliers for GF(2m)
Design of multipliers for GF(2m)
- Author(s): Z. Mao ; G. Shou ; Y. Hu ; Z. Guo
- DOI: 10.1049/el.2010.0246
For access to this article, please select a purchase option:
Buy article PDF
Buy Knowledge Pack
IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.
Thank you
Your recommendation has been sent to your librarian.
- Author(s): Z. Mao 1 ; G. Shou 1 ; Y. Hu 1 ; Z. Guo 1
-
-
View affiliations
-
Affiliations:
1: School of Information and Communication Engineering, Beijing University of Posts and Telecommunications, Beijing, People's Republic of China
-
Affiliations:
1: School of Information and Communication Engineering, Beijing University of Posts and Telecommunications, Beijing, People's Republic of China
- Source:
Volume 46, Issue 6,
18 March 2010,
p.
419 – 420
DOI: 10.1049/el.2010.0246 , Print ISSN 0013-5194, Online ISSN 1350-911X
A new design of multipliers for GF(2m) based on combination of bit-serial and bit-parallel schemes with low complexity is proposed. Using pipeline architecture, the scheme yields significantly lower latency compared to known bit-parallel multipliers for GF(2m).
Inspec keywords: logic design; multiplying circuits; Galois fields; pipeline processing
Other keywords:
Subjects: Algebra; Logic and switching circuits; Logic circuits; Logic design methods; Digital circuit design, modelling and testing; Parallel architecture; Algebra
References
-
-
1)
- A. Reyhani-Masoleh , A. Hasan . Low complexity bit parallel architecture for polynomial basis multiplication over GF (2m). IEEE Trans. Comput. , 8 , 945 - 959
-
2)
- M. Elia , M. Leone , C. Visentin . Low complexity bit-parallel multipliers for GF(2m) with generator polynomial xm+xk+1. Electron. Lett. , 7 , 551 - 552
-
3)
- B. Sunar , C.K. Koc . Mastrovisto multiplier for all trinomials. IEEE Trans. Comput. , 5 , 522 - 527
-
4)
- R. Lidl , H. Niederreiter . (1994) Introduction to finite fields and their applications.
-
5)
- C.W. Chiou , L.C. Lin , F.H. Chou , S.F. Shu . Low-complexity finite field multiplier using irreducible trinomials. Electron. Lett. , 24 , 1709 - 1711
-
6)
- R. Katti , J. Brennan . Low complexity multiplication in a finite field using ring representation. IEEE Trans. Comput. , 4 , 418 - 427
-
7)
- C.Y. Lee . Low complexity bit-parallel systolic multiplier over GF(2m) using irreducible trinomials. IEEE Proc., Comput. Digit. Tech. , 1 , 39 - 42
-
8)
- H. Wu . Bit-parallel finite field multiplier and square using polynomial basis. IEEE Trans. Comput. , 7 , 750 - 758
-
9)
- P.K. Meher . Systolic and non-systolic scalable modular designs of finite field multipliers for Reed-solomon codec. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 6 , 747 - 757
-
10)
- S.A. Vanstone , P.C. Oorschot . (1989) An introduction to error correcting codes with applications.
-
11)
- Ç.K. Koç , B. Sunar . Low-complexity bit-parallel canonical and normal basis multipliers for a class of finite fields. IEEE Trans. Comput. , 3 , 353 - 356
-
12)
- Mastrovito, E.D.: `‘VLSI designs for multiplication over finite field, GF(2', Proc. Sixth Int'l Conf., (AAECC-6), July 1988, Rome, Italy, p. 297–309.
-
13)
- P.K. Meher . Systolic and super-systolic multipliers for finite field. GF(2m) based on irreducible trinomials. IEEE Trans. Circuits Syst. , 4 , 1031 - 1040
-
1)
Related content
