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Fully-gated ground 10T-SRAM bitcell in 45 nm SOI technology

Fully-gated ground 10T-SRAM bitcell in 45 nm SOI technology

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A novel 10T-SRAM employing a fully-gated grounding scheme (10T-RGND) to limit a memory bitcell (MC) subthreshold leakage current (IOFF) in a 45 nm SOI technology is presented. The source voltage of the read-port of 10T-RGND is selectively grounded by a row decoder only when it is accessed, while those of inactive MCs are forced to a supply voltage (VDD). The number of stackable MCs per bitline (BL) of 10-RGND is increased by 10×, 40%, and 3.5× compared to the conventional 6T, the leakage current-compensating 8T (8T-LC), and the conventional 10T, respectively, at 1.0 V, 125°C, and fast corner process. The total leakage current of 10T-RGND is 6% less than 8T-LC, 17% less than 10T, but 22% larger than 6T in simulation.

References

    1. 1)
      • Alvandpour, A.: `Bitline leakage equalization for sub-100nm caches', Proc. 29th European Solid-State Circuit Conf., 2003, Estoril, Portugal, p. 401–404.
    2. 2)
      • Noguchi, H.: `Which is the best dual-port SRAM in 45-nm process technology? – 8T, 10T single end, and 10T differential', IEEE Int. Conf. on Integrated Circuit Design and Technology and Tutorial, Grenoble, France, 2008, p. 55–58.
    3. 3)
      • Chang, L.: `Stable SRAM cell design for the 32 nm node and beyond', IEEE Symp. on VLSI Technology, 2005, Kyoto, Japan, p. 128–129.
    4. 4)
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