Your browser does not support JavaScript!

Robust derivative superposition method for linearising broadband LNAs

Robust derivative superposition method for linearising broadband LNAs

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A linearisation methodology for broadband low noise amplifiers (LNAs) is considered. The proposed scheme is composed of the main transistor operating in strong inversion healed by a couple of auxiliary transistors operating in triode and subthreshold regions. The nonlinearities of these transistors graciously and efficiently compensate each other, improving main transistor linearity by over 10 dB over all corners for input signals as large as −14 dBm. Power consumption increases by 6% while frequency response and input impedance are almost not affected because the compensating circuits are quite small compared with the main device. Simulation results show that the compensated LNA implemented in Jazz-Semiconductor 0.18 µm CMOS technology has a gain of 11.3 dB, IIP3=18.4 dBm, BW=3.6 GHz while drawing 7.4 mA from a 2.4 V supply voltage.


    1. 1)
      • Qu, G., Parker, A.E.: `Analysis of inter modulation nulling in HEMT's', Optoelectronics and Microelectronic Materials and Devices Conf., December 1996, Canberra, Australia, p. 227–230.
    2. 2)
    3. 3)
      • Tanaka, S., Behbahani, F., Abidi, A.A.: `A linearization technique for CMOS RF power amplifiers', Symp. on VLSI Circuits, Dig. Tech. Pprs, 1997, Kyoto, Japan.
    4. 4)
    5. 5)
      • Perumana, B.G., Zhan, J.-H.C., Taylor, S., Laskar, J.: `A 12 mW, 7.5 GHz bandwidth, inductor less CMOS LNA for low-power, low-cost, multi-standard receivers', Proc. IEEE RFIC Symp., 2007, Honolulu, HI, USA, p. 57.
    6. 6)
      • T.W. Kim , B. Kim , K. Lee . Highly linear receiver front-end adopting MOSFET transconductance linearisation by multiple gated transistors. IEEE J. Solid-State Circuits , 1 , 223 - 229
    7. 7)
      • Zhan, J.-H.C., Taylor, S.: `A 5 GHz resistive-feedback CMOS LNA for low-cost multi-standard application', IEEE ISSCC Tech. Dig., 2006, San Francisco, CA, USA, p. 200.
    8. 8)
      • Aparin, V., Brown, G., Larson, L.E.: `Linearization of CMOS LNA's via optimum gate biasing', IEEE Int. Circuits System Symp., May 2004, Vancouver, BC, Canada, IV, p. 748–751.
    9. 9)
    10. 10)
      • B. Kim , J.-S. Ko , K. Lee . A new linearisation technique for MOSFET RF amplifier using multiple gated transistors. IEEE Microw. Guid. Wave Lett. , 9 , 371 - 373
    11. 11)
      • Chehrazi, S., Mirzaei, A., Bagheri, R., Abidi, A.A.: `A 6.5 GHz wideband CMOS low noise amplifier for multi-band use', Proc. IEEE Custom Integrated Circuits Conf., September 2005, San Jose, CA, USA, p. 801–804.
    12. 12)
      • J.C. Pedro , J. Perez . Design techniques for low in-band intermodulation distortion amplifiers. Microw. J. , 94 - 104
    13. 13)

Related content

This is a required field
Please enter a valid email address