Post-silicon timing yield enhancement using dual-mode elements

Post-silicon timing yield enhancement using dual-mode elements

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A simple but effective technique for timing yield enhancement is presented. The proposed technique tunes circuit timing using dual-mode elements, which are special logic gates that can change delay–leakage characteristics at the post-silicon level. In experiments using the ISCAS-85 benchmarks, the proposed technique reduced the timing failure rate by 59.52% on average.


    1. 1)
      • M. Mani , A. Devgan , M. Orshansky , Y. Zhan . A statistical algorithm for power- and timing-limited parametric yield optimization of large integrated circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 10 , 1790 - 1802
    2. 2)
      • M. Anis , M. Elmasry . (2003) Multi-threshold CMOS digital circuits – managing leakage power.
    3. 3)
      • Cao, Y., Sato, T., Orshansky, M., Sylvester, D., Hu, C.: `New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation', Proc. IEEE Custom Integrated Circuits Conf., 2000, p. 201–204.
    4. 4)
      • H.S. Park , W. Kim , D.J. Hyun , Y.H. Kim . Timing criticality for timing yield optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. , 12 , 3497 - 3505

Related content

This is a required field
Please enter a valid email address