© The Institution of Engineering and Technology
An accumulator-based digital-to-frequency (DFC) converter employing redundant signed binary addition (RSBA) is presented. RSBA is advantageous in that no carry propagation occurs resulting in constant delay regardless of operand word size. Utilising RSBA in the proposed DFC resolves the performance bottleneck in the DFC's conventional implementation and achieves extremely high frequency resolution. In addition, a new RSBA-based 8∶1 multiplexer is introduced for a complete RSBA implementation of the DFC. Experimental results show an increase of more than 3.5 times in the speed of the accumulator compared to the conventional implementation regardless of bit size of the adder.
References
-
-
1)
-
L. Xiu
.
The concept of time-average-frequency and mathematical analysis of flying-adder frequency synthesis architecture.
IEEE Circuit Syst. Mag.
,
27 -
51
-
2)
-
H. Ling
.
High speed binary adder.
IBM J. Res. Dev.
,
156 -
166
-
3)
-
M. Lehman ,
N. Burla
.
Skip techniques for high-speed carry propagation in binary arithmetic circuits.
IRE Trans. Electron. Comput.
,
691 -
698
-
4)
-
T.F. Ngai ,
M.J. Irwin ,
S. Rawat
.
Regular, area-time efficient carry-look-ahead adders.
J. Parallel Distrib. Comput.
,
92 -
105
-
5)
-
L. Xiu ,
Z. You
.
A flying-adder architecture of frequency and phase synthesis with scalability.
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
,
5 ,
637 -
649
-
6)
-
L. Xiu
.
A flying-adder on-chip frequency generator for complex SoC environment.
IEEE Trans. Circuits Syst.
,
12 ,
1067 -
1071
-
7)
-
M. Thornton
.
A signed binary addition circuit based on an alternative class of addition tables.
Comput. Electr. Eng.
,
2 ,
303 -
315
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2009.0823
Related content
content/journals/10.1049/el.2009.0823
pub_keyword,iet_inspecKeyword,pub_concept
6
6