http://iet.metastore.ingenta.com
1887

Redundant signed binary addition based digital-to-frequency converter

Redundant signed binary addition based digital-to-frequency converter

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

An accumulator-based digital-to-frequency (DFC) converter employing redundant signed binary addition (RSBA) is presented. RSBA is advantageous in that no carry propagation occurs resulting in constant delay regardless of operand word size. Utilising RSBA in the proposed DFC resolves the performance bottleneck in the DFC's conventional implementation and achieves extremely high frequency resolution. In addition, a new RSBA-based 8∶1 multiplexer is introduced for a complete RSBA implementation of the DFC. Experimental results show an increase of more than 3.5 times in the speed of the accumulator compared to the conventional implementation regardless of bit size of the adder.

References

    1. 1)
      • L. Xiu . The concept of time-average-frequency and mathematical analysis of flying-adder frequency synthesis architecture. IEEE Circuit Syst. Mag. , 27 - 51
    2. 2)
      • L. Xiu . A flying-adder on-chip frequency generator for complex SoC environment. IEEE Trans. Circuits Syst. , 12 , 1067 - 1071
    3. 3)
    4. 4)
      • M. Lehman , N. Burla . Skip techniques for high-speed carry propagation in binary arithmetic circuits. IRE Trans. Electron. Comput. , 691 - 698
    5. 5)
      • H. Ling . High speed binary adder. IBM J. Res. Dev. , 156 - 166
    6. 6)
      • T.F. Ngai , M.J. Irwin , S. Rawat . Regular, area-time efficient carry-look-ahead adders. J. Parallel Distrib. Comput. , 92 - 105
    7. 7)
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2009.0823
Loading

Related content

content/journals/10.1049/el.2009.0823
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address