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Low-jitter design method based on ωn-domain jitter analysis for 10 Gbit/s clock and data recovery ICs

Low-jitter design method based on ωn-domain jitter analysis for 10 Gbit/s clock and data recovery ICs

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A low-jitter design method based on ωn-domain jitter analysis for the clock and data recovery (CDR) ICs using the linear phase-locked loop (PLL) is proposed. Using this method, the loop parameters of the PLL can be optimised, which makes it possible to design the CDR IC for various targets.

References

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      • R.E. Best . (1984) Phase-locked loops.
    2. 2)
      • F.M. Gardner . (1979) Phaselock techniques.
    3. 3)
      • M. Mansuri , C.-K.K. Yang . Jitter optimization method based on phase-locked loop design parameters. J. Solid State Circuits , 11 , 1375 - 1382
    4. 4)
      • ‘Types and characteristics of SDH network protection architectures’, ITU-T Recommendation G.841.
    5. 5)
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      • E. Heirer , G. Wanner . (1996) Analysis by its history.
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2009.0717
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