Transistor variability after CHC and NBTI stress in 90 nm pMOSFET technology

Transistor variability after CHC and NBTI stress in 90 nm pMOSFET technology

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

An investigation is conducted of mismatching properties after channel hot carrier (CHC) and negative bias temperature instability (NBTI) stress is observed using pMOSFETs of various device sizes from 90 nm CMOS technology. The purpose of this study is to analyse the mismatching of transistor pairs after the foregoing reliability tests. Degradations of the pMOSFETs are extracted by measuring variations of Vtlin and Idsat before and after stress. The experiments show that CHC mode is more serious than that of NBTI mode. The probable mechanism of the transistor mismatches is due to the random generation traps in the gate dielectric (SiON) and at the interface between SiON/Si-bulk. Furthermore, the results suggest that CHC involves the integration of HC and NBTI effects induced transistor mismatches, particularly for small size devices.


    1. 1)
      • K.R. Lakshmikumar , R.A. Hadaway , M.A. Copeland . Characterization and modeling of mismatch in MOS transistors for precision analog design. IEEE J. Solid-State Circuits , 6 , 1057 - 1066
    2. 2)
    3. 3)
      • Lovett, S.J., Cllancy, R., Welten, M., Mathewson, A., Mason, B.: `Characterizing the mismatch of submicron MOS transistors', IEEE Int. Conf. on Microelectronic Test Structures, March 1996, 9, p. 39–42.
    4. 4)
      • M. Conti , P. Crippa , S. Orcioni , C. Turchetti . Layout-based statistical modeling for the prediction of the matching properties of MOS transistors. IEEE Trans. Circuits Syst., Fundam. Theory Appl , 5 , 680 - 685
    5. 5)
      • Chen, Y., Zhou, J., Tedja, S., Hui, F., Oates, A.S.: `Stress-induced MOSFET mismatch for analog circuits', IEEE Int. Integrated Reliability Workshop, (IIRW), Final Report, 2001, p. 41–43.
    6. 6)
      • S.Y. Chen , J.C. Lin , H.W. Chen , H.C. Lin , Z.W. Jhou , S. Chou , J. Ko , T.F. Lei , H.S. Huang . Mismatches after hot-carrier injection in advanced complementary metal–oxide–semiconductor technology particularly for analog applications. Jpn. J. Appl. Phys. , 3266 - 3271
    7. 7)
      • S.Y. Chen , C.H. Tu , J.C. Lin , M.C. Wang , P.W. Kao , M.H. Lin , S.H. Wu , Z.W. Jhou , S. Chou , J. Ko , H.S. Huang . Investigation of DC hot-carrier degradation at elevated temperatures for p-channel metal–oxide–semiconductor field-effect transistors of 0.13 µm technology. Jpn. J. Appl. Phys , 3 , 1527 - 1531
    8. 8)
      • C.H. Tu , S.Y. Chen , M.H. Lin , Z.Y. Hsieh , M.C. Wang , S.H. Wu , S. Chou , J. Ko , H.S. Huang . The switch of the worst case on NBTI and hot carrier reliability for 0.13 µm pMOSFETs. Appl. Surf. Sci , 19 , 6186 - 6189
    9. 9)
      • S. Pae , J. Maiz , C. Prasad , B. Woolery . Effect of BTI degradation on transistor variability in advanced semiconductor technologies. IEEE Trans. Device Mater. Reliab. , 3 , 519 - 525

Related content

This is a required field
Please enter a valid email address