http://iet.metastore.ingenta.com
1887

Optimisation of direct auto-zeroing offset cancellation in low voltage applications using dual level CMFB

Optimisation of direct auto-zeroing offset cancellation in low voltage applications using dual level CMFB

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A modified CMFB circuit is presented that reinstates the use of direct opamp auto-zeroing offset cancellation techniques in low voltage applications. This approach is particularly useful for high precision sample and hold amplifiers and Nyquist rate ADCs, where the opamp is reset during one of the clock phases. Differential offsets up to 50 mV are effectively reduced as demonstrated by a sample and hold example.

References

    1. 1)
    2. 2)
      • Hernes, B.: `A 1.2V 220MS/s 10b pipeline ADC implemented in 0.13 µm digital CMOS', ISSCC Dig. Tech. Pprs, February 2004, San Fransisco, CA, USA, p. 256–258.
    3. 3)
      • Geelen, G.: `A 90 nm CMOS 1.2 V 10b power and speed programmable pipelined ADC with 0.5 pJ/conversion-step', ISSCC Dig. Tech. Pprs, February 2006, San Fransisco, CA, USA, p. 782–791.
    4. 4)
      • Boulemnakher, M.: `A 1.2 V 4.5 mW 10b 100 MS/s pipeline ADC in a 65 nm CMOS', ISSCC Dig. Tech. Pprs, February 2008, San Fransisco, CA, USA, p. 250–252.
    5. 5)
      • Garrity, D., Rakers, P.: `Common-mode output sensing circuit', US Patent No. 5894284, 1999, Apr. 13.
    6. 6)
http://iet.metastore.ingenta.com/content/journals/10.1049/el.2009.0500
Loading

Related content

content/journals/10.1049/el.2009.0500
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address