High-speed and low-power FeRAM utilising merged BL/PL array architecture with twin-bitline-driven scheme

High-speed and low-power FeRAM utilising merged BL/PL array architecture with twin-bitline-driven scheme

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A novel design method for nonvolatile ferroelectric random access memory (FeRAM) using a merged bitline(BL)/plateline(PL) array architecture with a twin bitline-driven scheme is proposed. This method is effective in improving the FeRAM performance and reduces the power consumption. A 128 Kbit FeRAM prototype applying the proposed circuitry is implemented. The chip size, access time and memory array power dissipation are reduced to about 87, 44 and 15.8%, respectively, in comparison with those of conventional FeRAM.


    1. 1)
      • A. Sheikholeslami , P.G. Gulak . A survey of circuit innovations in ferroelectric random-access memories. Proc. IEEE , 667 - 689
    2. 2)
    3. 3)
      • Koike, H.: `A 60 ns 1 Mb nonvolatile ferroelectric memory with non-driven cell plate line write/read scheme', ISSCC Tech. Dig., 1996, p. 368–369.
    4. 4)
      • Hirano, H.: `2 V/100 ns 1T/1C nonvolatile ferroelectric memory architecture with bitline driven read scheme and non-relaxation reference cell', VLSI Circuits Dig. Tech. Pprs, 1996, p. 48–49.
    5. 5)
      • Kang, H.-B.: `A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on 1T1C FeRAM', VLSI Circuits Dig. Tech. Pprs, 2001, p. 125–126.

Related content

This is a required field
Please enter a valid email address