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High-speed and low-power FeRAM utilising merged BL/PL array architecture with twin-bitline-driven scheme

High-speed and low-power FeRAM utilising merged BL/PL array architecture with twin-bitline-driven scheme

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A novel design method for nonvolatile ferroelectric random access memory (FeRAM) using a merged bitline(BL)/plateline(PL) array architecture with a twin bitline-driven scheme is proposed. This method is effective in improving the FeRAM performance and reduces the power consumption. A 128 Kbit FeRAM prototype applying the proposed circuitry is implemented. The chip size, access time and memory array power dissipation are reduced to about 87, 44 and 15.8%, respectively, in comparison with those of conventional FeRAM.

References

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      • A. Sheikholeslami , P.G. Gulak . A survey of circuit innovations in ferroelectric random-access memories. Proc. IEEE , 667 - 689
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      • Koike, H.: `A 60 ns 1 Mb nonvolatile ferroelectric memory with non-driven cell plate line write/read scheme', ISSCC Tech. Dig., 1996, p. 368–369.
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      • Hirano, H.: `2 V/100 ns 1T/1C nonvolatile ferroelectric memory architecture with bitline driven read scheme and non-relaxation reference cell', VLSI Circuits Dig. Tech. Pprs, 1996, p. 48–49.
    5. 5)
      • Kang, H.-B.: `A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on 1T1C FeRAM', VLSI Circuits Dig. Tech. Pprs, 2001, p. 125–126.
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