access icon free A 16-bit Hybrid ADC with Circular-Adder-Based Counting for 15μm Pitch 640×512 LWIR FPAs

A hybrid Analog to digital converter (ADC) is presented for long-wave infrared focal plane arrays. A two-stage quantization structure is applied in the folding integration process, which results in better chargehandling capacity and higher linearity compared with conventional designs while using fewer transistors at the pixel level. By employing a circular-adder-based counting structure with 3T dynamic memory cells, hardware consumption can be reduced. A pixel circuit of pitch 15μm has been designed using the 0.18mm Complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the pixel-level ADC is 0.214μW, and the charge-handling capacity is 1Ge-. Simulation results demonstrate a signal-to-noise ratio of 90dB and a nonlinearity of 0.11%.

Inspec keywords: power consumption; readout electronics; analogue-digital conversion; CMOS integrated circuits; adders; focal planes; infrared detectors

Other keywords: power 0.214 muW; dynamic memory cells; folding integration process; hybrid ADC; size 0.18 mum; power consumption; hybrid analog to digital converter; complementary metal-oxide-semiconductor process; charge-handling capacity; CMOS process; circular-adder-based counting; LWIR FPA; long-wave infrared focal plane arrays; pixel-level ADC; hardware consumption; two-stage quantization structure

Subjects: Signal processing and conditioning equipment and techniques; Logic circuits; Logic and switching circuits; Counting circuits and electronics for particle physics; A/D and D/A convertors; Photodetectors; CMOS integrated circuits; A/D and D/A convertors

http://iet.metastore.ingenta.com/content/journals/10.1049/cje.2020.01.006
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content/journals/10.1049/cje.2020.01.006
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