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A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25Gb/s-6.25Gb/s SerDes

A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25Gb/s-6.25Gb/s SerDes

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The paper presents a fully integrated multiphase output low-jitter CMOS phase-locked loop for 1.25Gb/s to 6.25Gb/s wireline SerDes transmitter clocking. The self-biased bandwidth technology with simplified structure is applied to reduce the sensitivity to process variations. A diffierential Charge pump (CP) which is suitable for low power supply and process migration is proposed. An accelerator is built to avoid the disadvantage of great damping factor. Self-adaptive frequency dividers are used to improve power efficiency. The simulation results under 65nm and 55nm process almost maintain almost the same jitter performance and show the high process insensitivity and good jitter performance.

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