Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

A Reconfigurable Hardware Architecture for Packet Processing

A Reconfigurable Hardware Architecture for Packet Processing

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Chinese Journal of Electronics — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In this paper, we propose a reconfigurable packet processing hardware architecture for future switch,in which several protocol-independent action units are introduced to remove the protocol dependence of conventional packet processors. With the proposed architecture, any specified header fields can be mapped into the right action unit, so that the processor can meet any packet processing demands. To reduce the hardware resource cost, the processor cost model and optimization algorithm are proposed. The NetFPGA-based implementation shows a throughput of 94Gb/s with 64-B packets. The programmability cost is approximately 1.5 times of conventional design, which consumes only 8% of the total FPGA resources.

http://iet.metastore.ingenta.com/content/journals/10.1049/cje.2017.08.018
Loading

Related content

content/journals/10.1049/cje.2017.08.018
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address