access icon free XY -Type GPU Cache: Exploiting Spatial Localities in both X and Y Directions to Avoid Conflict Miss

Cache has been introduced into many Graphics processing units (GPUs) to decrease the frequency of data transfer between high-performance computing units and low-speed long-latency external memory. The traditional index mapping scheme designed originally for CPU cache exploits only the spatial locality in address space. The access to graphics data always has region locality on the frame buffer: there are high spatial localities in both X and Y directions. It may generate more conflict misses on some limited cache lines, which eventually results in high cache miss ratio and a performance drop. Traditional CPU cache cannot be used directly in GPU. We propose a new conflict-avoiding GPU cache called XY - type cache with a new index mapping scheme, whose cache line indices are computed from both X and Y coordinates of pixels and the cache index distribution is consistent with the region locality on the frame buffer. Our evaluation results show that the proposed XY -type GPU cache can reduce cache miss ratio by 88% at most via scattering the cache accesses to all lines evenly, and can completely avoid the bad effect caused by frame resolution. Since the cache miss ratio in direct-mapped or 2-way set-associative structure is approximate to or even lower than that in fully-associative structure which is the best case in terms of lowering cache line conflicts, XY -type GPU cache can be designed with lower complexity and lower consumption power.

Inspec keywords: graphics processing units; cache storage

Other keywords: XY-type GPU cache; high performance computing units; cache index distribution; cache line indices; cache miss ratio; conflict-avoiding GPU cache; spatial localities; index mapping scheme; long latency external memory; frame buffer; conflict miss; graphics data; graphics processing units; CPU cache; data transfer

Subjects: Memory circuits; Semiconductor storage; Microprocessor chips; Microprocessors and microcomputers

http://iet.metastore.ingenta.com/content/journals/10.1049/cje.2015.01.015
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content/journals/10.1049/cje.2015.01.015
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