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5th IEE International Conference on ADDA 2005. Advanced A/D and D/A Conversion Techniques and their Applications

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  • Location: Limerick, Ireland
  • Conference date: 25-27 July 2005
  • ISBN: 0 86341 542 3
  • Conference number: CP510
  • The following topics are dealt with: advanced converter techniques; power line application; digital CMOS technology; digital-to-analog converter; broadband communication; professional radio application; ADC nonlinearities; multichannel antenna array; digitiser system; mobile communication; satellite communication; wireless receiver; pipeline ADC; data acquisition system; wideband CDMA; low-power continuous-time delta-sigma modulator; MATLAB-SIMULINK toolbox; PWM feedback; pole-zero cancellation effect; open-loop residue amplifier; VDSL; debugging tool; CIC decimation filter; micromachined sensor; GSM; ENOB; fading channel

1 - 20 of 59 items found

  • An architecture for a reconfigurable charge summation based ADC
  • Noise and error shaping for video applications pipeline ADC optimisation techniques
  • A low-power high precision self-testing data acquisition system for a large seismic exploration grid
  • Systematic top-down design of a low-power continuous-time delta-sigma modulator wideband CDMA
  • A Matlab/SIMULINK toolbox for the simulation-based high-level synthesis of Nyquist-rate data converters-application to a pure digital 0.13 μm CMOS [email protected] MS/s analog front-end for PLC/VDSL
  • A GmC filter design methodology for high-speed continuous time-delta A/D converters in 90 nm standard CMOS
  • Comparison of algorithms for computing INL from sinewave histogram
  • Sigma delta's capacity to measure
  • Noise analysis for high order electromechanical sigma-delta modulators
  • Design of a 1.8 V, 10-bit 130+MS/s time-interleaved non-scaled pipeline ADC in 0.18 μm CMOS
  • A CMOS high-resolution automotive sensor A/D interface based on a [email protected] kS/s programmable-gain cascade 2-1 sigma- delta modulator embedded design-for-testability strategies
  • Effect of a PWM feedback DAC on the noise and linearity of a delta-sigma ADC
  • A 100 dB SNR sigma-delta ADC with 2.5 MSPS output data rate and on-chip reference and input buffers
  • Synthesis of the noise transfer function in N-path sigma delta modulators
  • A dynamic element matching scheme for quadrature sigma-delta modulators
  • Pole-zero cancellation effects in the design of continuous-time sigma delta converters
  • Exploiting SiGe BiCMOS technology in the design of A12-B 200-MS/S pipeline ADC
  • Design of low-voltage low-power pipeline ADCs using a single-phase scheme
  • Self-adjusting bias current technique in flexible ADCs for mixed-signal SoC platforms
  • New static and dynamic digital error correction and adaptation techniques for SAR and pipeline AD converters
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