Irish Signals and Systems Conference 2004
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- Location: Belfast, Ireland
- Conference date: 30 June-2 July 2004
- ISBN: 0 86341 440 0
- Conference number: CP506
- The following topics are dealt with: embedded FPGAs for SoC platforms; space-time singular value decomposition; networked computer control; digital signal processing; optical storage; watermarking; speech enhancement; speech processing; epileptic electroencephalogram; schizophrenia research; linear predictive speech coding; network analysis; analogue and mixed signal circuits; bandpass sigma-delta modulator; CMOS circuits; control systems and modelling; IEEE 802.11b wireless networks; communication signal processing; adaptive filters; adaptive echo cancellation; time hopping ultra wideband systems; audio processing; audio coding; WLAN; WiFi and GPRS; face recognition; direct sequence code division multiple access; WCDMA channel emulator; wireless fair queuing; advanced control systems; prostate cancer diagnosis; computer-aided seizure detection; virtual engineering; brain activity monitoring; wave energy converter; enuresis treatment device; milk pasteurisation plant; Bluetooth security; optical coherence tomography; ad-hoc network test-bed; image and multidimensional signal processing; medical images; face detection; encryption; digital circuits; mobile communications; image processing circuits; circuit modelling; signal estimation tools
1 - 20 of 118 items found
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Improved speech analysis for glottal excited linear predictive speech coding
- Author(s): A. Olatunji and P. Murphy
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We describe a new method for extracting the voice source and vocal tract impulse response from voiced speech for glottal excited linear predictive speech coding. The method utilises a mixed phase model of speech and dynamic gain control to deconvolve speech signals into source and filter components. Voiced speech segments are analysed for pitch synchronously and coded with a glottal codebook of 32 entries, while the processing of unvoiced speech and silence intervals is done with a stochastic codebook. The method also exploits a high correlation among glottal pulses to simplify the algorithm computational complexity and to improve codebook search time. Results of coding both male and female speech with the new method are presented.
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Describing function approximation for biomedical engineering applications
- Author(s): O. Kinnane ; J. Ringwood ; D. Kelly ; S. Malpas
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The paper focuses on the determination of suitable approximations for sigmoid-type nonlinear characteristics, which are common to physiological systems, particularly cardiovascular regulatory systems. These sigmoid nonlinearities have been implicated in the development of limit cycle oscillations in blood pressure. Approximations of the sigmoid are required since the describing function is not calculable for all the representations of the sigmoid characteristic. We present a new approximation, which gives a better overall approximation of the sigmoid and, hence, can assist the use of describing functions in the diagnostic analysis of cardiovascular function.
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Chopping of phase frequency detector to remove static phase offset in PLLs and MDLLs
- Author(s): I.M. Kennedy and J. Horan
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The paper describes a number of modifications to a standard phase frequency detector (PFD) that improve static phase offset (SPO) in both phase locked loops (PLLs) and multiplying delay locked loops (MDLLs). It then details a chopping methodology that eliminates SPO caused by timing mismatches in the PFD and charge pump (CP). The improvement that this method has on MDLL period jitter is also explained with supporting data from a 0.13 μm test chip.
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Design of an efficient interface between an FPGA and external memory
- Author(s): F. Crowe ; A. Daly ; T. Kerins ; W. Marnane
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The interface between an FPGA core design and its communicating system is often the limiting factor in achieving high performance. The paper looks at how the memory interface logic can be separated from the core design, allowing the cores to run at frequencies greater than the maximum memory access frequency. FIFO memory blocks are used as buffers to transfer data between different clock domains. An application example implementing a number of encryption algorithms on an FPGA is provided. The complete design is prototyped on a PCI accelerator card containing a Xilinx Virtex-E2000 FPGA and SRAM memory banks.
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Arbitrary order charge approximation event driven phase lock loop model
- Author(s): B. Daniels ; R. Farrell ; G. Baldwin
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An alternative technique for the derivation of an event driven phase lock loop (PLL) model is presented, enabling the modelling of higher order PLLs. Event driven models have previously been developed for 2nd, and 3rd order PLLs (Hedayat,C.D. et al., 1997; 1999; Van Paemel, M., 1994), however, for higher order systems (5th, 6th etc.), the derivation of the loop filter difference equations is not amenable. The paper introduces a technique to model PLLs with arbitrary order filters that removes the restriction on the loop order.
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Approximate rotations architecture design for SVD/QRD
- Author(s): K. Dickson ; Z. Liu ; J. McCanny
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A silicon implementation of the approximate rotations algorithm capable of carrying the computational load of algorithms such as QRD (QR decomposition) and SVD (singular value decomposition) is described. The original approximate rotations algorithm has been modified in order to simplify the method of optimal angle selection. The silicon design studies undertaken provide direct practical evidence of superior performance with the approximate rotations algorithm, requiring approximately 40% of the total computation time of the conventional CORDIC algorithm, for a similar silicon area cost.
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An architecture for network analysis and emulation
- Author(s): J. Lynch and H. Melvin
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Packet delay, delay variation (jitter) and packet loss affect the performance of all Internet applications but particularly that of real-time multimedia. Developers of such applications or of multimedia delivery protocols need to be able to test them extensively before they are deployed on the Internet. We describe an architecture that combines both network analysis and network emulation. The network analysis module captures, stores and analyses network characteristics between two Internet hosts for the purpose of modeling. Models representing the network condition to be emulated can be constructed from this data or other sources by the network emulation module. This enables various Internet conditions to be recreated in a local controlled environment facilitating extensive testing of new applications and protocols.
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Analysis of data sets using trio sonification
- Author(s): C. Cullen and E. Coyle
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Sound and audio play a far greater part in our daily working lives than ever before. Mobile phone ring tones are now based upon polyphonic music sequences that allow relatively complex audio to be generated from a handset to convey information (e.g. a call or message is incoming). This real world example of sonification suggests that far more could be made of sonification techniques for analysis - particularly in the business environment where applications could deliver information while other tasks are being performed in tandem. For the definition of the basic principles of trio sonification, an application is being developed to read in data sets of certain formats (.csv or xml) and allow the various elements to be sonified for analysis. Existing work suggests that many data elements can be conveyed within a single sonification and this lends itself to analysis that seeks to take a broader assessment of a complete set of data. Although the application is still in the development stage, the techniques it employs require consideration in their own right - notably the use of rhythmic parsing to allow the conveyance of far greater levels of data using sound. It has been found that orchestration in general is of prime importance in effective and transparent data sonification and to this end the instrumentation and rhythmic arrangement of such data for analysis is effectively as much a technique in its own right as the sonification itself.
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A novel tag sorting architecture for SoC implementation of a WFQ scheduler
- Author(s): K. McLaughlin and S. Sezer
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The ordered retrieval of finishing tags is an issue of critical importance for the next generation of multi-gigabit IP packet schedulers. Following a discussion of the complexities involved, a recommendation is made for the use of a longest prefix matching, sort and store technique, conventionally used in IP routing lookups. This offers a solution fast enough for multi-gigabit line speeds and is specifically targeted for hardware implementation.
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Improving robustness of non-linear side-informed watermarking using turbo codes
- Author(s): K.M. Whelan ; G.C.M. Silvestre ; N.J. Hurley ; F. Balado
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The application of turbo coding to non-linear side-informed watermarking schemes is examined. The proposed system is viewed as a serial concatenation of two codes. The outer code is a variable rate turbo code while the inner code involves our previously proposed side-informed embedding scheme which may be understood as a repetition code. For a fixed system code rate, we evaluate the robustness of the proposed scheme, in terms of bit error rate (BER), when subjected to a number of attacks. The performance is compared with another side-informed embedding scheme, spread-transform dither modulation (ST-DM) in the case of both additive and amplitude scaling attacks.
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Fast bit reversal scrambling on the TigerSHARC
- Author(s): N.A. Pilz ; B. Doherty ; K. Adamson
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Many versions of the fast Fourier transformations require a re-ordering of data in either the pre- or postprocessing phases. It is claimed that the unscrambling of data in higher level languages, such as C, can often take 10% to 50% of the total computation for many FFT algorithms (Burrus, C.S., 1988). The paper considers code optimisation using the TigerSHARC processor developed by Analog Devices. In many algorithms, the equilibrium between data access and computation is such that 128-bit access and stores are required to keep the computational units active (Analog Devices Technical Note EE-147). This is particularly obvious with bit reversal. Short vector word loading and scalar storing can lead to significant under-utilisation of processing resources. The paper implements optimised assembly code that uses both short vector memory loading and storing of data to improve cycle counts dramatically. The implementation of a hand optimised bit reversal routine is compared with compiler friendly C code optimised by the VisualDSP3.0 compiler. It is demonstrated that C compiler technology cannot achieve peak computing rates and that intimate knowledge of the underlying hardware is needed to achieve optimal performance.
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An investigation into the shared buffer architecture for SoC implementation
- Author(s): S. O'Kane and S. Sezer
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The asynchronous nature of packet based communication demands efficient management of buffer resources at network nodes. Shared buffer architectures consequently become one of the dominating constructs of modern routers and switches. The paper investigates new and existing shared buffer architectures that are suitable for the emerging SoC technologies.
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A low voltage 5 GHz fourth-order LC bandpass sigma-delta modulator
- Author(s): T. Carey ; K.G. McCarthy ; P.J. Murphy
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The paper details the design of a fourth-order continuous-time bandpass ΣΔ modulator. This modulator is implemented in a 0.25 μm SiGe HBT BiCMOS process, with an fT of 47 GHz. Simulations predict 33 dB SNR in a 4 MHz bandwidth converting a 1.25 GHz signal with a sampling frequency of 5 GHz. The circuit draws 24 mA from a 2.5 V supply.
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Precision CMOS oscillator design
- Author(s): K. Berney and K. Deevy
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The humble oscillator is a ubiquitous circuit, contained in many electronic systems. A temperature independent, fully monolithic, CMOS oscillator that has a reduced process sensitivity is presented. Temperature independence is achieved via a novel zero temperature coefficient current source and, when implemented correctly, the primary source of deviation in the oscillation frequency is the process variation in the mobility of silicon. The oscillator is implemented in a 0.7 μm analogue CMOS process.
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CMOS transimpedance amplifier for use with multiple APD geometries
- Author(s): D. O'Connell and A.P. Morrison
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A transimpedance amplifier (TIA) capable of meeting the 500 MHz bandwidth requirement of IEEE1394 using avalanche photodiodes of any diameter from 20 μm to 250 μm is presented. A range of different sized photodiodes were simulated with the transimpedance amplifier using Agilent's ADS and the AustriaMicroSystems (AMS) 0.6 μm CMOS process. The feedback resistor of the TIA is varied to maintain a consistent 500 MHz bandwidth, independent of the detector size. The simulations predict a transimpedance gain of 354 Ω for 250 μm diameter detectors and 507 Ω for 20 μm diameter detectors at the 500 MHz bandwidth.
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A high sensitivity CMOS photoreceiver incorporating a high multiplication gain avalanche photodiode
- Author(s): A. Moloney and A. Morrison
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A photoreceiver consisting of a monolithically integrated avalanche photodiode and a CMOS transimpedance amplifier is presented. The sensitivity has been analysed theoretically through simulations and a detailed noise analysis. Sensitivity results are presented based on the OEIC being fabricated in a 1.5 μm CMOS process. At 2 Gb/s, the receiver has sensitivities of -33.5 dBm and -34.7 dBm for 650 nm and 850 nm light respectively, which exceed the performance of other reported CMOS photoreceivers.
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Advanced control of an industrial grinding process
- Author(s): J.J. Govindhasamy ; S.F. McLoone ; G.W. Irwin ; J.J. French ; R.P. Doyle
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The paper describes the development of a linear time series prediction model for an industrial aluminium substrate disk grinding process. Using historical grindstone performance data, a linear model is developed which provides a one-step-ahead prediction of the removal rate based on the previous removal rates. This model is then used to develop a direct inverse model and internal model controller. Preliminary plant investigations suggest that thickness defects can be reduced by 50% or more when the model based controllers are employed.
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Perceptual based analysis of the Concord algorithms for intra-talkspurt playout delay adaptation
- Author(s): M.K. Ranganathan and L. Kilmartin
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The Concord mechanism (Sreenan, C.J. et al., IEEE Trans. Multimedia, vol.2, no.2, p.88-100, 2000) was developed as an efficient solution for playout delay adaptation in voice over IP (VoIP) networks. Playout delay adaptation techniques are used in real time voice communication over packet-switched networks to compensate for the effect of network jitter at the receiver. The performance of algorithms such as Concord is often analysed based on statistical metrics such as the mean buffering delay and average packet loss rates suffered. However, an analysis of the resulting voice quality achieved would present a more holistic view of the performance of a playout delay adaptation technique. An in-depth analysis of the Concord algorithms from a voice quality perspective is presented. Measured Internet network delays are used in the analysis where the resultant voice quality is measured using PESQ, the ITU-T P.862 objective voice quality measurement algorithm.
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Stochastic search in data-based modelling of dynamic systems
- Author(s): S. Butler and J. Ringwood
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The paper compares the application of two stochastic search techniques for the solution of two typical problems in modelling nonlinear systems using a multi-modelling approach: interpolation function determination; linear model structure determination. It is shown that the two candidate stochastic search techniques employed, genetic algorithms and swarm intelligence, show different advantages for each of the problems considered.
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Co-simulation framework for a networked control system within an IEEE 802.11b wireless network
- Author(s): J. Colandairaj ; W.G. Scanlon ; G.W. Irwin
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With recent interest in controlling physical systems using standard communications protocols, there is need for accurate network modelling to study the dynamics between network protocols and control systems. To bridge this gap, the modelling framework for a C MEX S-function to work with Simulink® that emulates a networked control system with mixed-traffic stations on an 802.11 wireless network is presented. The programming architecture for the simulator and issues concerning inter-communication between simulations are discussed in detail.
