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2010 Forum on Specification & Design Languages (FDL 2010)

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  • Location: Southampton, UK
  • Conference date: 14-16 Sept. 2010
  • ISBN: 978 2 95305 043 1
  • Conference number: 2010/002
  • The following topics are dealt with: formal verification; debugging; performance optimisation; power optimisation; robustness; formal models; SystemC models; mixed-technology system design; SoC synthesis; model driven approaches; and time modelling.

1 - 20 of 52 items found

  • LBSD1: Inheritance and Modelling
  • Modeling time-triggered architecture based safety-critical embedded systems using SystemC
  • A solution to the lack of multiple inheritance in SystemVerilog
  • Feature-oriented refactoring proposal for transaction level models in SoCLib
  • ABD1: Formal Models for Verification and Debug
  • Complete verification of weakly programmable IPs against their operational ISA model
  • Evaluating debugging algorithms from a qualitative perspective
  • Mapping of concurrent object-oriented models to extended real-time task networks
  • LBSD2: Power and Performance Optimisation
  • A tripartite system level design approach for design space exploration
  • Towards an ESL framework for timing and power aware rapid prototyping of HW/SW systems
  • Reconstructing line references from optimized binary code for source-level annotation
  • ABD Tutorial: Robustness
  • Early robustness evaluation of digital integrated systems
  • Bounded fault tolerance checking
  • Robustness with respect to error specifications
  • ABD+LBSD: Formal Models for Design Analysis
  • Formal support for untimed SystemC specifications. Application to high-level synthesis
  • Formal verification of timed VHDL programs
  • Tiny-π: a novel formal method for specification. Analysis, and verification of dynamic partial reconfiguration processes
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