IEE Colloquium on Advanced MOS and Bi-Polar Devices

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  • Location: London, UK
  • Conference date: 14 Feb. 1995
  • Conference number: 1995/033
  • The following topics were dealt with: bipolar transistors and technology; BiCMOS structures; MOS transistors and technology

17 items found

  • Prospects for the exploitation of SiGe technologies
  • P+/N shallow junctions formation on Ge+ preamorphized silicon substrate
  • The current status of plasma grown silicon dioxide layers on SiGe epitaxial layers for surface passivation and possible gate oxide application
  • Reverse heterojunction engineering: a novel technique for the suppression of the parasitic bipolar transistor in deep sub-micron MOSFETs
  • Temperature characterisation and parameter extraction for fine-geometry CMOS processes
  • Advanced process development using numerical simulation
  • Automating the calculation of 3D interconnect parasitics
  • Innovative process architectures for rapid cycle-time sub 0.5 μm CMOS
  • Process sensitivity analysis using design of experiments and full 2D TCAD simulations
  • LPCVD SiGe for heterojunction bipolar transistors
  • Improved base current ideality in polysilicon emitter bipolar transistors by fluorine implantation
  • The bonded wafer silicon on insulator approach to high performance low power integrated circuits
  • Parasitic current mechanisms and current stress induced degradation effects in mesa-isolated, SiGe heterojunction bipolar transistors
  • Improved modelling and parameter extraction for parasitic BJT devices in CMOS
  • Radiation effects on advanced bipolar and MOS devices
  • Electromigration simulations for small scale structures
  • On-line characterisation of metallic micro contamination for ULSI microelectronics
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