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Affiliations:
1:
Department of Electrical Engineering, Jadavpur University , Kolkata-700032 , India ;
2:
Department of Electrical Engineering, Mizoram University , Aizawl-796004 , India
Source: Michael Faraday IET International Summit 2020 (MFIIS 2020),
2021
p.
19 – 22
Neutral Point Clamped (NPC) inverter has attracted special attention in the field of medium voltage drives and Electric Vehicle (EV) applications. In conventional three- or higher-level NPC topologies, the issues related to the higher harmonic content and electromagnetic interference (EMI) stresses on the semiconductor switches, still exist. This paper proposes a modified pulse-width modulation (PWM) control technique for multi-level NPC inverters, which is proficient in reducing the harmonic content from the inverter voltage and thereby improves the power quality of the EV system. An FPGA-based pre-formulated harmonic reduction (HR) algorithm is introduced in this work to decrease the EMI stresses of the power switches and to improve the overall efficiency of the inverter. The experimental findings of the proposed control scheme hold strong alignment with the theoretical and simulated outcomes.