With the need of rapid detection of ships or other iso-time-sensitive targets, a block parallel processing technology based on multiple FPGA was proposed, which realized the parallelization of the estimation of typical sea clutter model parameters and CFAR ship detection algorithm. In order to realize azimth-oriented pipelined processing, the SAR image with a large width in a SAR aperture was divided into 16 sub-block SAR images along the range direction for parallel processing. Each sub-block SAR image was taken as a parallel processing unit in FPGA, and the sea clutter model parameters in it were independently calculated. To further improve the efficiency of parallel processing, each sub-block SAR image adopted 8-way parallel processing channel for rapid processing, so as to achieve rapid estimation of sea clutter model parameters and real-time ship detection. Through theoretical analysis, this technique could meet the time-efficiency requirement of real-time pipelined processing for spaceborne SAR ship detection. Experiments on the ship detection performance of a parallel processing unit using the actual spaceborne SAR image data shown that the technique maintained the same detection performance compared with traditional CPU computing platform.