A single chip architecture for multiprocessor DSP
A single chip architecture for multiprocessor DSP
- Author(s): C.I. Brown ; N.A. Thacker ; R.B. Yates
- DOI: 10.1049/ic:19950779
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- Author(s): C.I. Brown ; N.A. Thacker ; R.B. Yates Source: IEE Colloquium on `Multiprocessor DSP (Digital Signal Processing) - Applications, Algorithms and Architectures', 1995 page ()
- Conference: IEE Colloquium on `Multiprocessor DSP (Digital Signal Processing) - Applications, Algorithms and Architectures'
Inspec keywords: matrix multiplication; random-access storage; cache storage; CMOS digital integrated circuits; parallel architectures; digital signal processing chips; sparse matrices; multiprocessing systems; wavelet transforms
Subjects: Parallel architecture; Microprocessors and microcomputers; CMOS integrated circuits; Digital signal processing chips; Signal processing and detection; Multiprocessing systems; Digital signal processing