Proposed architecture of configurable, adaptable SoC
Proposed architecture of configurable, adaptable SoC
- Author(s): J. Kadlec ; M. Danek ; L. Kohout
- DOI: 10.1049/cp:20080690
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- Author(s): J. Kadlec ; M. Danek ; L. Kohout Source: IET Irish Signals and Systems Conference (ISSC 2008), 2008 p. 368 – 373
- Conference: IET Irish Signals and Systems Conference (ISSC 2008)
- DOI: 10.1049/cp:20080690
- ISBN: 978-0-86341-931-7
- Location: Galway, Ireland
- Conference date: 18-19 June 2008
- Format: PDF
To study the concept of Self Adaptive Networked computing Elements (SANE) we developed a configurable platform based on the Xilinx EDK and Xilinx System Generator tools. The platform is built around a MicroBlaze CPU with a set of standard peripherals such as DDR RAM controller and RS232 interface - denoted as "Master", extended with a set of several "reprogrammable Accelerators" connected to the MicroBlaze "Master" via fast simplex links (FSL).
Inspec keywords: peripheral interfaces; system-on-chip; DRAM chips; reconfigurable architectures
Subjects: Microprocessors and microcomputers; Computer architecture; Microprocessor chips; Memory circuits; Peripheral interfaces; Semiconductor storage
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