The application of a single-phase scheme to low-voltage pipeline ADCs designed in standard CMOS technologies is described. In order to validate the theoretical findings and assess the performance of the proposed technique, a 10-bit 4 MS/s pipeline ADC was fully designed and simulated, first with all switches driven by a conventional six-phase clock generator, and after with only a single-phase scheme. Simulated results show the signal integrity and overall performance are preserved, pointing to the use of simpler low-voltage circuits and avoiding the complexity as well as the problems normally created by the use of non-overlapping clock generators.