The interface between an FPGA core design and its communicating system is often the limiting factor in achieving high performance. The paper looks at how the memory interface logic can be separated from the core design, allowing the cores to run at frequencies greater than the maximum memory access frequency. FIFO memory blocks are used as buffers to transfer data between different clock domains. An application example implementing a number of encryption algorithms on an FPGA is provided. The complete design is prototyped on a PCI accelerator card containing a Xilinx Virtex-E2000 FPGA and SRAM memory banks.