A parallel architecture for general predictive control is presented which has a number of advantages for VLSI implementation over those previously published. It has a regular structure with identical processing cells which can be implemented in fixed point, or floating point, or a hybrid arithmetic. Data can be extracted and controlled easily. The controller includes an effective regularisation scheme which allows a priori information about the plant and the controller to be included and kept permanently present in the identification scheme. Users can select the level of the influence of this a priori information on the controller adaptation relative to the effect of the measured data. The resultant architecture is suitable for fixed-point VLSI, or DSP, application aiming for low-power and minimal complexity, or maximal speed.