Task-processor mapping for real-time parallel systems using genetic algorithms with hardware-in-the-loop
Task-processor mapping for real-time parallel systems using genetic algorithms with hardware-in-the-loop
- Author(s): M.J. Baxter ; M.O. Tokhi ; P.J. Fleming
- DOI: 10.1049/cp:19951042
For access to this article, please select a purchase option:
Buy conference paper PDF
Buy Knowledge Pack
IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.
1st International Conference on Genetic Algorithms in Engineering Systems: Innovations and Applications (GALESIA) — Recommend this title to your library
Thank you
Your recommendation has been sent to your librarian.
- Author(s): M.J. Baxter ; M.O. Tokhi ; P.J. Fleming Source: 1st International Conference on Genetic Algorithms in Engineering Systems: Innovations and Applications (GALESIA), 1995 p. 158 – 163
- Conference: 1st International Conference on Genetic Algorithms in Engineering Systems: Innovations and Applications (GALESIA)
This paper discusses the application of genetic algorithms (GAs) to the challenging problem of task to processor mapping in the field of real-time parallel processing. Mapping is the off-line allocation of the tasks that represent a parallelised algorithm across a multi-processor architecture. Here, the objective of the optimisation process is to tune the mapping in order to minimise the algorithm cycle time. This paper examines a GA approach for this, and applies it to the mapping of a number of demanding real-time control algorithms. Initially, a simple parallel architecture model is used as the objective function. This leads to the embedding of the target hardware within the objective function, to improve the performance of the GA. The effectiveness of these GA approaches are compared to the results of simple heuristic. Further enhancements in the GA, such as integrating financial cost in the optimisation process and the determination of an optimal parallel architecture, are finally discussed.
Inspec keywords: processor scheduling; parallel architectures; genetic algorithms; real-time systems
Subjects: Multiprocessing systems; Parallel architecture; Optimisation techniques; Distributed systems software
Related content
content/conferences/10.1049/cp_19951042
pub_keyword,iet_inspecKeyword,pub_concept
6
6