Animate vision demonstrator utilising reconfigurable system designs
Animate vision demonstrator utilising reconfigurable system designs
- Author(s): A.J. Shelley and N.L. Seed
- DOI: 10.1049/cp:19950709
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- Author(s): A.J. Shelley and N.L. Seed Source: Fifth International Conference on Image Processing and its Applications, 1995 p. 500 – 504
- Conference: Fifth International Conference on Image Processing and its Applications
- DOI: 10.1049/cp:19950709
- ISBN: 0 85296 642 3
- Location: Edinburgh, UK
- Conference date: 4-6 July 1995
- Format: PDF
The justifications for migration from discrete logic implementations to field programmable devices (PLD/FPGA) for state machine, logic replacement and datapath operations are well known and established. They offer the user a flexible design methodology at a gate level for a low initial investment and demand no early commitments to high volumes. Furthermore, the capabilities of a volatile static memory based FPGA technology extend well beyond the limited scope of integration enhancement. This paper outlines a reconfigurable image processing architecture (RIPA) and its integration into an animate vision demonstrator.
Inspec keywords: SRAM chips; computer vision; field programmable gate arrays; computer animation; reconfigurable architectures
Subjects: Computer vision and image processing techniques; Semiconductor storage; Logic and switching circuits; Semiconductor integrated circuits; Parallel architecture; Logic circuits; Memory circuits; Optical information, image and video signal processing; Graphics techniques
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